I’ve been looking at noise from different angles and the result is a new firmware release for the TCD1304 driver.
There are few important changes, like new GPIOs for the connection to the CCD and I will update the tcd1304.wordpress.com site in the coming days.
If you cannot wait, everything (I hope) is of course documented in the source code.
And below are the boring details:
1: Crosstalk between analog and digital lines
I have no idea how the circuit is laid out inside the STM32F401RE, but on the outside it looks like this:
The previous firmwares had output on PA0 and PA1. Right next to Vref+ and Vref- which the ADC measures input against. The alternate-function mapping didn’t allow for moving the output on PA1, but the output on PA0 has now been moved to a physically more distant GPIO. For reasons I can’t remember I also moved fM away from PA6.
PA0, PC2 PB0 and PB2 are now pulled down and can be connected to GND to make for a virtual ground at GPIOs around the ADC and the noisy high frequency fM.
2: Speed limits
The GPIO speed has been limited to 25 MHz for all communication and driving pulses.
3: Typical CCD driving and ADC sampletime
The datasheet for the TCD1304 specifies 2.0 MHz as the typical master clock. I have no idea if driving at other frequencies will degrade the performance of the CCD, but the fM has now been increased from 1.4 to 2.0 MHz.
The fM is now defined in main.h and the clocks and periods for the timers for all the other driving pulses are derived from this. You can even change the system core clock and still have proper output, because fM-period is calculated from the APB1-clock,
On the same note the ADC sampletime has been increased from 3 ADC clockcycles to 15.
4: Proper flushing
Obviously this gives a cleaner everything. Seriously though, with proper attention to the pulse sequences just before data-acquisition, the linear CCD module performs much better.
5: Bug fixed
The annoying bug described in the previous post has been squashed. Still the occasional connection issue persists.