Despite the silly title, the work behind this post was quite tedious. I’ve been asked to do an advanced science project for the students at my high school, and what better than to have the little ones construct a spectrograph (this is not the tedious part, but it’s for another post).
To this end I’ve redesigned the PCB for the TCD1304 to make it more student friendly. It really just means that I’ve replaced the 10-pin IDC connector with a 6-pin 2.54mm Mini-PV connection. Oh yeah and the TO-92 2SA1015 transistor has been replaced with the same in an SOT-23 housing. And here it is:
To really make it easy for the kids I also remapped the GPIOs in the UART firmware, so they only have to put their greasy little fingers on two connectors on the nucleo side of the wire:
After assembling 7 boards for the students, I immediately and for a reason I don’t remember decided it was time to learn KiCAD.
The result was a new PCB for the TCD1304 with an option for an on-board low-noise low drop-out voltage regulator (LT1761). It’s really small. Well, it’s 12% smaller than the board for the students:
Unfortunately I’ve run out of 90° angle connectors, so the wire is soldered directly on the board and covers everything new in the circuit.
I had great expectations for a lower noise level, but apparently the LDO makes little difference:
However, I wasn’t just interested in the performance of the the fancy new LDO-circuit, I was also curious how the student-friendly firmware would fare. I was expecting a fair amount of cross-talk now that all the noisy digital lines were so close to ADC-in.
I was expecting something like this:
But it turned out not to be a problem, at least not every time. After swapping boards back and forth innumerable times, I realized I was seeing this pattern only with an SH-period of 25. There’s nothing stupid (or magical) about the number 25, but it’s uneven and all the other SH-periods I was trying out were even.
And sure enough, even SH-periods eliminate the noise:
Here is the pattern again:
I did this many more time (this was the tedious part I promised).
The firmware doesn’t perform any math on the SH-period except for one place: When adjusting the SH-pulse after reconfiguring the timers before a new integration.
The universal cure (besides the trivial answer of using only even SH-periods) is to subtract the modulo 2 of the SH-period when adjusting the SH-pulse.
Thank you for listening. Updates to the firmware will be published in the downloads section on tcd1304.wordpress.com as soon as I have verified on the scope, that the modulo 2 trick is indeed a good idea.
The new PCB can be found at the dirtyPCB store.
Handling uneven SH-periods by subtracting modulo 2 of SH-period from the SH-delay, cause the driving pulses to violate the timing requirements. It does however appear to work, but occasionally more noise is seen.
For these reasons I’ve not implemented it the firmware, and the recommendation is instead to choose the nearest even integer.